Multiple-gate transistor structure and method for fabricating

ABSTRACT

A multiple-gate transistor structure which includes a substrate, source and drain islands formed in a portion of the substrate, a fin formed of a semi-conducting material that has a top surface and two sidewall surfaces, a gate dielectric layer overlying the fin, and a gate electrode wrapping around the fin on the top surface and the two sidewall surfaces separating source and drain islands. In an alternate embodiment, a substrate that has a depression of an undercut or a notch in a top surface of the substrate is utilized.

FIELD OF THE INVENTION

[0001] The present invention generally relates to a multiple-gatetransistor and method for fabricating and more particularly, relates toa multiple-gate semiconductor structure equipped with a gate electrodethat wraps around a semiconductor fin on its top and sidewall surfacesseparating a source and a drain region of the transistor and method forfabricating the structure.

BACKGROUND OF THE INVENTION

[0002] As the gate length of the MOSFET is scaled down into the sub-50nm regime for improved performance and density, the requirements forbody-doping concentration, gate oxide thickness, and source/drain (S/D)doping profiles to control short-channel effects become increasinglydifficult to meet when conventional device structures based on bulksilicon (Si) substrates are employed. The heavy channel doping requiredto provide adequate suppression of short-channel effects results indegraded mobility a n d enhanced junction leakage. The aggressivereduction of the silicon dioxide SiO₂ gate dielectric thickness forreduced short-channel effects and improved drive current leads toincreased direct tunneling gate leakage current and standby powerconsumption, and also raises concerns regarding the gate oxidereliability. For device scaling well into the sub-50 nm regime, apromising approach to controlling short-channel effects is to use analternative device structure with multiple-gates, such as thedouble-gate and the surround-gate or wrap-around gate structure.

[0003] A simple example of a multiple-gate device is the double-gateMOSFET structure, where there are two gate electrodes on the opposingsides of the channel. There are several ways in which a double-gatestructure can be implemented. One way is the vertical-channeldouble-gate MOSFET. This is described by U.S. Pat. No. 6,372,559 B1issued to Crowder et al. for a method of fabricating a self-alignedvertical double-gate MOSFET, and by U.S. Pat. No. 6,406,962 B1 issued toAgnello et al. for a vertical trench-formed dual-gate FET devicestructure and method for fabrication. A common feature of these twomethods is that the source-to-drain direction is oriented normal to theplane of the substrate surface, and the gate-to-gate direction isparallel to the plane of the substrate surface. The device fabricationprocesses for such a double-gate structure are typically complicated,costly and suffer from poor manufacturability.

[0004] Another method to fabricate a double-gate MOSFET is described byU.S. Pat. No. 6,413,802 B1 issued to Hu et al. for fin FET transistorstructures having a double gate channel extending vertically from asubstrate and methods for manufacture. In U.S. Pat. No. 6,413,802 B1,the device channel comprises a thin silicon fin formed on an insulativesubstrate (e.g., silicon oxide) and defined using an etchant mask. Gateoxidation is performed, followed by gate deposition and gate patterningto form a double-gate structure overlying the sides of the fin. Both thesource-to-drain direction and the gate-to-gate direction are in theplane of the substrate surface. This device structure is widelyrecognized to be one of the most manufacturable double-gate structures.An integral feature of the double-gate MOSFET described in U.S. Pat. No.6,413,802 B1 is the etchant mask on the silicon fin. The retention ofthe etchant mask is crucial due to problems faced in the etch process,particularly relating to the etch selectivity of the gate electrode withrespect to the gate dielectric during the gate patterning step.

[0005] It is therefore an object of the present invention to provide amultiple-gate transistor structure and a method for fabricating thestructure that allows transistor scaling beyond the limits of theconventional bulk silicon MOSFET.

SUMMARY OF THE INVENTION

[0006] In accordance with the present invention, a multiple-gatesemiconductor structure and a method for fabricating the structure areprovided.

[0007] In a preferred embodiment, a multiple-gate semiconductorstructure is provided which includes a substrate; source and drainislands formed in a portion of the substrate; a fin formed of asemi-conducting material having a top surface and two sidewall surfacesconnecting the semiconductor source and drain islands; a gate dielectriclayer overlying the fin; and a gate electrode wrapping around the fin onthe top surface and the two sidewall surfaces of the fin separating thesource and drain islands.

[0008] In the multiple-gate semiconductor structure, the semiconductingmaterial may be silicon, or may be silicon and germanium. The fin may berounded at two top corners. The gate dielectric layer may includesilicon oxide, silicon oxynitride, or a high permittivity materialselected from the group consisting of La₂O₃, HfON, Al₂O₃, HfO₂ and ZrO₂.The relative permittivity of the high permittivity material may be atleast 5. The gate dielectric layer may have a thickness between 3 Å and100 Å. The gate dielectric layer may have a first thickness on the finsidewall surfaces and a second thickness on the fin top surface, whereinthe first thickness is different from the second thickness. The secondthickness may be smaller than the first thickness. The gate dielectriclayer may have a thickness on the top surface of the fin less than 20 Å.

[0009] The gate electrode may be formed of poly-crystalline silicon, ormay be formed of poly-crystalline silicon germanium, or may be formed ofa metal. The source and drain islands each may include a lightly dopedor extension region. The source and drain islands may be strapped by aconductive material selected from the group consisting of metals andsuicides. Contacts between the conductive material and the source anddrain islands are made on at least one of the sidewall and top surfacesof the fin.

[0010] The present invention is further directed to a multiple-gatesemiconductor structure that includes a substrate that has a depressionin a top surface, the depression includes an undercut or a notch; a finformed of a semi-conducting material and has a top surface and twosidewall surfaces, the fin is positioned vertically juxtaposed to thedepression in the top surface of the substrate; source and drain regionsformed in the semi-conducting material of the fin; a gate dielectriclayer overlying the fin; and a gate electrode wrapping around the fin onthe two sidewall surfaces, the top surface and a bottom of a base of thefin separating the source and drain regions.

[0011] In the multiple-gate semiconductor structure, the semiconductingmaterial may include silicon, or may include silicon and germanium. Thefin may be rounded at two top corners, or may have two square corners.The gate dielectric layer may include silicon oxide, may include siliconoxynitride, or may include a high permittivity material selected fromthe group consisting of La₂O₃, HfON, Al₂O₃, HfO₂ and ZrO₂. The relativepermittivity may be at least 5. The gate dielectric layer may have athickness between 3 Å and 100 Å. The gate dielectric layer may have afirst thickness on the fin sidewall surfaces and a second thickness onthe fin top surface, wherein the first thickness may be different fromthe second thickness. The second thickness may be smaller than the firstthickness. The gate dielectric layer may have a thickness on the topsurface of the fin less than 20 Å.

[0012] In the multiple-gate semiconductor structure, the gate electrodemay include poly-crystalline silicon, may include poly-crystallinesilicon germanium, or may include a metal. The source and drain islandsmay each include a lightly doped or extension region. The source anddrain islands may be strapped by a conductive material selected from thegroup consisting of metals and silicides. Contacts between theconductive material and the source and drain islands may be made on atleast one of the sidewall and top surfaces of the fin.

[0013] The present invention is still further directed to a method forfabricating a multiple-gate semiconductor structure which includes thesteps of providing a substrate that includes a semi-conducting layeroverlying an insulating layer; patterning and forming a fin in thesemi-conducting layer, the fin has two sidewall surfaces and a topsurface; depositing a layer of a dielectric material overlying the fin;depositing a layer of a conductive material overlying the layer ofdielectric material; patterning the layer of conductive material forminga gate straddling across the two sidewall surfaces and the top surfaceof the fin; and forming a source and a drain region in thesemi-conducting layer.

[0014] The method for fabricating a multiple-gate semiconductorstructure may further include the step of forming the semi-conductingsubstrate in a material including silicon, or in a material includingsilicon and germanium. The method may further include the step offorming the layer of dielectric material in silicon oxide. The finforming process may further include a fin surface smoothing step,wherein the fin surface smoothing step may further include sub-steps ofsacrificial oxidation and high temperature annealing in a hydrogenambient. The method may further include the step of forming thedielectric layer in a material including silicon oxide, or siliconoxynitride, or a high permittivity material selected from the groupconsisting of La₂O₃, HfON, Al₂O₃, HfO₂ and ZrO₂. The high permittivitymaterial may have a relative permittivity of at least 5.

[0015] The method may further include the step of forming the gatedielectric layer to a thickness between 3 Å and 100 Å. The method mayfurther include the step of forming a different thickness of thedielectric layer on the sidewall surfaces and on the top surface of thefin, or the step of forming the gate dielectric layer to a smallerthickness on the top surface of the fin compared to the gate dielectriclayer on the sidewall surfaces of the fin. The method may furtherinclude the step of forming the gate dielectric layer on the top surfaceof the fin to a thickness of less than 20 Å. The method may furtherinclude the step of forming the gate in a material includingpoly-crystalline silicon, or poly-crystalline silicon germanium. Themethod may further include the step of forming the source or drainregion in a lightly doped or extension region. The method may furtherinclude the step of forming a layer of a conductive material on top ofthe source and drain regions, or forming the layer of conductivematerial in a material selected from the group consisting of metal,metallic silicide and metallic nitride.

[0016] The present invention is still further directed to a method forfabricating a multiple-gate semiconductor structure that include thesteps of providing a substrate that includes a semi-conducting layeroverlying an insulating layer; patterning and forming a fin in thesemi-conducting layer, the fin has two sidewall surfaces and a topsurface; forming a depression in a top surface of the substrate at abase of the fin; depositing a layer of a dielectric material overlyingthe fin; depositing a layer of a conductive material overlying the layerof dielectric material; patterning the layer of conductive materialforming a gate straddling across the two sidewall surfaces and the topsurface of the fin; and forming a source and a drain region in thesemi-conducting layer.

[0017] The method for fabricating a multiple-gate semiconductorstructure may further include the step of forming the depression in thetop surface of the substrate by undercutting at the base of the fin, orthe step of forming the depression by undercutting using an etchprocess. The method may further include the step of forming a layer of aconductive material on top of the source and drain regions, or formingthe layer of conductive material selected from the group consisting ofmetal, metallic silicide and metallic nitride.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] These and other objects, features and advantages of the presentinvention will become apparent from the following detailed descriptionand the appended drawings in which:

[0019]FIGS. 1A, 1B and 1C are enlarged, perspective views illustrating afabrication process for the present invention multiple-gate structurewherein two silicon fins are patterned and formed on a substrate with aninsulating layer inbetween the fins and the substrate.

[0020]FIGS. 2A and 2B are enlarged, cross-sectional views illustratingthe shapes of the silicon fins having square corners and roundedcorners, respectively.

[0021]FIG. 3 is an enlarged, cross-sectional view illustrating analternate embodiment of the present invention wherein the buried oxidelayer under the silicon fins is undercut or notched by an etch process.

[0022]FIGS. 4A and 4B are illustrations of micrographs obtained in across-sectional transmission electron microscopy image.

[0023]FIGS. 5A and 5B are enlarged, plane views showing contact layoutsfor the present invention semiconductor structures.

[0024]FIGS. 6A and 6B are graphs illustrating drain current versus gatevoltage curves for the present invention multiple-gate N-channel andP-channel MOSFETs, respectively.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0025] The present invention relates to the field of semiconductordevices and to the manufacture of field effect transistors withmultiple-gates for scaling of the complementarymetal-oxide-semiconductor (CMOS) technology well into the sub-50nanometer (nm) regime.

[0026] Metal-oxide-semiconductor field effect transistor (MOSFET)technology is the dominant semiconductor technology used for themanufacture of ultra-large scale integrated (ULSI) circuits. Reductionin the side of MOSFETs has provided continued improvement in speedperformance, circuit density, and cost per unit function over the pastfew decades. As the gate length of the MOSFET is reduced, the source anddrain increasingly interact with the channel and gain influence on thechannel potential. Consequently, a transistor with a short gate lengthsuffers from problems related to the inability of the gate tosubstantially control the on and off states of the channel. Phenomenasuch as reduced gate control associated with transistors that have shortchannel lengths are termed short-channel effects. Increased body dopingconcentration, reduced gate oxide thickness, and ultra-shallowsource/drain junctions are ways to suppress short-channel effects.However, for device scaling well into the sub-50 nm regime, therequirements for body-doping concentration, gate oxide thickness, andsource/drain (S/D) doping profiles become increasingly difficult to meetwhen conventional device structures based on bulk silicon (Si)substrates are employed. The heavy channel doping required to provideadequate suppression of short-channel effects results in degradedmobility and enhanced junction leakage. The aggressive reduction of thesilicon dioxide SiO₂ gate dielectric thickness for reduced short-channeleffects and improved drive current leads to increased direct tunnelinggate leakage current and standby power consumption, and also raisesconcerns regarding the gate oxide reliability. Innovations in front-endprocess technologies or the introduction of alternative devicestructures are required to sustain the historical pace of scaling.

[0027] To extend the scalability of CMOS technology beyond thelimitations of the conventional bulk MOSFET and to realize the ultimatelimit of silicon MOSFETs, a multiple-gate device structure should beused. The introduction of additional gates improves the capacitancecoupling between the gates and the channel, increases the control of thechannel potential by the gate, helps suppress short channel effects, andprolongs the scalability of the MOS transistor.

[0028] In the present invention, a fabrication process that overcomesthe process difficulties faced in U.S. Pat. No. 6,413,802 is disclosedin which the use of an etchant mask after the fin formation process iseliminated. In addition, the process improvement to be described in thepresent invention method results in a multiple-gate structure thatsubstantially wraps around a silicon fin or a transistor channel. Themultiple-gate structure is superior in performance to those described inthe prior art references. Moreover, the fabrication process is superioror more manufacturable when compared to the prior art methods.

[0029] A process flow for fabricating the present inventionmultiple-gate structure 10 is schematically illustrated in FIGS. 1A, 1Band 1C. The silicon fins 12,14 are formed of a semi-conducting material,such as Si on top of an insulating material layer 16, i.e., buriedoxide, and patterned using an etchant mask (not shown). The etchant maskmay include a material commonly used for masking an etch process, suchas photoresist, silicon oxide, silicon nitride, etc. In a preferredembodiment, the etchant mask is silicon oxide. In the present inventionmethod, an optional fin surface smoothing step is used to improve orreduce the surface roughness of the fin sidewalls. When the etchant maskused for fin definition is silicon oxide, as in the preferredembodiment, it is removed either before or after the fin smoothingprocess. The removal of the etchant mask on the silicon fins 12,14 priorto gate dielectric 20 formation allows the device to have at least atriple-gate structure since the gate electrode 18 will finally be formedon each of the two sidewalls 22,24,26,28 as well as the top surfaces30,32 of the fins 12,14. If the etchant mask used for fin definition isa photoresist, it has to be removed before the fin surface smoothingstep to avoid the high temperatures used in the fin smoothing process.The fin surface smoothing is performed by subjecting the fins 12,14 to asacrificial oxidation and/or silicon sidewall treatment (e.g., hightemperature anneal at 1000° C. in H₂ ambient). The surface smoothing ofthe fin sidewalls contributes to the achievement of good carriermobilities. Depending on whether the silicon oxide etchant mask isremoved prior to the fin smoothing step, the shape of the fin may besquare-like or rounded at the top. This is illustrated in FIGS. 2A and2B.

[0030] In an alternate embodiment, the buried oxide 16 under the siliconfins 12, 14 is undercut or notched by using an etch process. The etchprocess can be a plasma etch or a wet etch using dilute hydroflouricacid (HF). The undercut 40 (or notch) of the substrate insulating layerunderlying the silicon fins 12, 14 allows the formation of anomega-shaped gate electrode 36 as depicted in FIG. 3. The feature allowsadditional capacitance coupling between the gate and the channelunderneath the fin, and the structure thus emulates a wrap-around gatebut avoids the process difficulties associated with the implementationof the wrap-around structure. The preceding description completes thefin formation.

[0031] The present invention process is followed by gate dielectric 38formation. The gate dielectric 38 may be formed by thermal oxidation,chemical vapor deposition, sputtering, etc. In general, the thickness ofthe gate dielectric may be different on the sidewalls 22,24,26,28 of thefin and the tops 30,32 of the fin. Depending on the technique of gatedielectric formation, the gate dielectric thickness on the tops 30,32 ofthe fin may be thinner than the thickness on the fin sidewalls22,24,26,28. In one embodiment, the gate dielectric thickness on the topsurfaces 30,32 of the fin is less than 20 Å. The gate dielectric mayinclude a conventional material such as silicon dioxide or siliconoxynitride with a thickness ranging from 3 Å to 100 Å, preferably 10 Åor less. The gate dielectric may also include a high permittivity(high-k) material such as aluminum oxide Al₂O₃ hafnium oxide HfO₂,zirconium oxide ZrO₂, with an equivalent oxide thickness of 3 Å to 100Å. A cross-sectional transmission electron spectroscopy (TEM) image ofthe silicon fin 12,14 after gate dielectric 38 formation is shown inFIG. 4A. The TEM image shows a fin that is 55 nm tall, 25 nm wide, andstands on an undercut buried oxide.

[0032] Next, the gate material 42 is deposited. The gate material may bepolycrystalline-silicon (poly-Si), poly-crystalline silicon germanium(poly-SiGe), a refractory metal such as molybdenum and tungsten,compounds such as titanium nitride, or other conducting materials. Agate mask (not shown) is defined and the underlying gate material 42 isetched to form the gate electrode 36. The gate etch stops on the gateoxide, and the gate is electrically isolated from the transistorstructure by the gate oxide. In the preferred embodiment, the gatematerial is poly-Si and the gate oxide is silicon oxynitride. A plasmaetch using chlorine and bromine chemistry may be used to achieve a highetch selectivity in excess of 2000. A high etch selectivity is criticalfor device structures with a tall fin and aggressively scaled gate oxidethickness. After the definition of the gate 50, the masking material canbe removed. The lightly-doped drain (LDD) or drain extension is formednext. This may be achieved by ion implantation, plasma immersion ionimplantation (PIII), or other techniques known and used in the art.Next, a spacer 48 is formed on each of the sidewalls 44,46 of the gate50 and the channel by deposition and selective etching of the spacermaterial. The spacer material may include a dielectric material such assilicon nitride or silicon dioxide as illustrated in FIG. 4B.

[0033] In the preferred embodiment, the spacer 48 is a siliconnitride/oxide composite spacer. After spacer 48 formation, source anddrain regions (not shown) are doped by ion implantation, PIII, gas orsolid source diffusion, or any other techniques known and used in theart. Any implant damage or amorphization can be annealed throughsubsequent exposure to elevated temperatures. The resistance of thesource, drain, and gate 50 can also be reduced by strapping the source,drain, and gate 50 with a conductive material. The conductive materialmay be a metallic silicide such as titanium silicide, cobalt silicide,or nickel silicide, a metallic nitride such as titanium nitride andtantalum nitride, a metal such as tungsten and copper, or a heavilydoped semiconductor such as n+ doped Si. In the preferred embodiment,the conductive material is cobalt silicide which may be formed by aself-aligned silicide (salicide) process. The cobalt-silicided poly-Sigate is shown in FIG. 4B. In the source and drain regions, theconductive material may be formed on both the top of the fin as well asthe sidewall of the fin.

[0034] Next, contacts are formed to the source, drain and gate regionsusing techniques known and used in the art. It is important to achieve avery low contact resistance in nanoscale devices. One way to reduce thecontact resistance is to increase the contact area by making contactwith the fin sidewall. The contact layout (top view) shown in FIGS. 5Aand 5B may be used.

[0035] In FIG. 6A, the drain current versus gate voltage of themultiple-gate N-channel and P-channel MOSFETs with gate lengths of 25 nmare shown. N+ and P+ dual poly-Si gates are adopted for N- and P-channelMOSFETs, respectively. At a supply voltage of 0.7 V, the drive currentsfor the N- and P-channel devices are 1300 mA/μm and 550 mA/μm,respectively, as shown in FIG. 6B. For a supply voltage of 1 V, in-situdoped N+ poly gate may be used for both the N- and P-channeltransistors.

[0036] While the present invention has been described in an illustrativemanner, it should be understood that the terminology used is intended tobe in a nature of words of description rather than of limitation.

[0037] Furthermore, while the present invention has been described interms of a preferred and an alternate embodiment, it is to beappreciated that those skilled in the art will readily apply theseteachings to other possible variations of the inventions.

[0038] The embodiment of the invention in which an exclusive property orprivilege is claimed are defined as follows.

What is claimed is:
 1. A multiple-gate semiconductor structurecomprising: a substrate; source and drain islands formed in a portion ofsaid substrate; a fin formed of a semi-conducting material having a topsurface and two sidewall surfaces; a gate dielectric layer overlyingsaid fin; and a gate electrode wrapping around said fin on said topsurface and said two sidewall surfaces separating source and drainislands.
 2. The multiple-gate semiconductor structure of claim 1,wherein said semi-conducting material comprises silicon.
 3. Themultiple-gate semiconductor structure of claim 1, wherein saidsemi-conducting material comprises silicon and germanium.
 4. Themultiple-gate semiconductor structure of claim 1, wherein said fin isrounded at two top corners.
 5. The multiple-gate semiconductor structureof claim 1, wherein said gate dielectric layer comprises silicon oxide.6. The multiple-gate semiconductor structure of claim 1, wherein saidgate dielectric layer comprises silicon oxynitride.
 7. The multiple-gatesemiconductor structure of claim 1, wherein said gate dielectric layercomprises a high permittivity material selected from the groupconsisting of La₂O₃, HfON, Al₂O₃, HfO₂ and ZrO₂.
 8. The multiple-gatesemiconductor structure of claim 1, wherein said high permittivitymaterial having a relative permittivity of at least
 5. 9. Themultiple-gate semiconductor structure of claim 1, wherein said gatedielectric layer having a thickness between 3 Å and 100 Å.
 10. Themultiple-gate semiconductor structure of claim 1, wherein said gatedielectric layer having a first thickness on said fin sidewall surfacesand a second thickness on said fin top surface, said first thicknessbeing different from said second thickness.
 11. The multiple-gatesemiconductor structure of claim 1, wherein said second thickness issmaller than said first thickness.
 12. The multiple-gate semiconductorstructure of claim 1, wherein said gate dielectric layer having athickness on the top surface of said fin less than 20 Å.
 13. Themultiple-gate semiconductor structure of claim 1, wherein said gateelectrode comprises poly-crystalline silicon.
 14. The multiple-gatesemiconductor structure of claim 1, wherein said gate electrodecomprises poly-crystalline silicon germanium.
 15. The multiple-gatesemiconductor structure of claim 1, wherein said gate electrodecomprises a metal.
 16. The multiple-gate semiconductor structure ofclaim 1, wherein said source and drain islands each comprises a lightlydoped or extension region.
 17. The multiple-gate semiconductor structureof claim 1, wherein said source and drain islands are strapped by aconductive material selected from the group consisting of metals andsilicides.
 18. The multiple-gate semiconductor structure of claim 17,wherein contacts between said conductive material and said source anddrain islands are on at least one of the sidewall and top surfaces ofthe fin.
 19. A multiple-gate semiconductor structure comprising of: asubstrate having a depression in a top surface, said depressioncomprises an undercut or a notch; a fin formed of a semi-conductingmaterial having a top surface and two sidewall surfaces, said fin beingpositioned vertically juxtaposed to said depression in said top surfaceof the substrate; source and drain regions formed in saidsemi-conducting material of said fin; a gate dielectric layer overlyingsaid fin; and a gate electrode wrapping around said fin on said twosidewall surfaces, said top surface, and a bottom of a base of said finseparating said source and drain regions.
 20. The multiple-gatesemiconductor structure of claim 19, wherein said semi-conductingmaterial comprises silicon.
 21. The multiple-gate semiconductorstructure of claim 19, wherein said semi-conducting material comprisessilicon and germanium.
 22. The multiple-gate semiconductor structure ofclaim 19, wherein said fin is rounded at two top corners.
 23. Themultiple-gate semiconductor structure of claim 19, wherein said gatedielectric layer comprises silicon oxide.
 24. The multiple-gatesemiconductor structure of claim 19, wherein said gate dielectric layercomprises silicon oxynitride.
 25. The multiple-gate semiconductorstructure of claim 19, wherein said gate dielectric layer comprises ahigh permittivity material selected from the group consisting of La₂O₃,HfON, Al₂O₃, HfO₂ and ZrO₂.
 26. The multiple-gate semiconductorstructure of claim 25, wherein said high permittivity material having arelative permittivity of at least
 5. 27. The multiple-gate semiconductorstructure of claim 19, wherein said gate dielectric layer having athickness between 3 Å and 100 Å.
 28. The multiple-gate semiconductorstructure of claim 19, wherein said gate dielectric layer having a firstthickness on said fin sidewall surfaces and a second thickness on saidfin top surface, said first thickness being different from said secondthickness.
 29. The multiple-gate semiconductor structure of claim 19,wherein said second thickness is smaller than said first thickness. 30.The multiple-gate semiconductor structure of claim 19, wherein said gatedielectric layer having a thickness on the top surface of said fin lessthan 20 Å.
 31. The multiple-gate semiconductor structure of claim 19,wherein said gate electrode comprises poly-crystalline silicon.
 32. Themultiple-gate semiconductor structure of claim 19, wherein said gateelectrode comprises poly-crystalline silicon germanium.
 33. Themultiple-gate semiconductor structure of claim 19, wherein said gateelectrode comprises a metal.
 34. The multiple-gate semiconductorstructure of claim 19, wherein said source and drain islands eachcomprises a lightly doped or extension region.
 35. The multiple-gatesemiconductor structure of claim 19, wherein said source and drainislands are strapped by a conductive material selected from the groupconsisting of metals and suicides.
 36. The multiple-gate semiconductorstructure of claim 19, wherein contacts between said conductive materialand said source and drain islands are on at least one of the sidewalland top surfaces of the fin.
 37. A method for fabricating amultiple-gate semiconductor structure comprising the steps of: providinga substrate comprising a semi-conducting layer overlying an insulatinglayer; patterning and forming a fin in said semi-conducting layer, saidfin having two sidewall surfaces and a top surface; depositing a layerof a dielectric material overlying said fin; depositing a layer of aconductive material overlying said layer of dielectric material;patterning said layer of conductive material forming a gate straddlingacross said two sidewall surfaces and said top surface of the fin; andforming a source and drain region in said semi-conducting layer.
 38. Themethod of claim 37 further comprising the step of forming saidsemi-conducting layer in a material comprising silicon.
 39. The methodof claim 37 further comprising the step of forming said semi-conductinglayer in a material comprising silicon and germanium.
 40. The method ofclaim 37 further comprising the step of forming said layer of dielectricmaterial in a material comprising silicon oxide.
 41. The method of claim37, wherein said fin forming step further comprising a fin surfacesmoothing step.
 42. The method of claim 41, wherein said fin surfacesmoothing step further comprising sub-steps of sacrificial oxidation andhigh temperature annealing in a hydrogen ambient.
 43. The method ofclaim 37, further comprising the step of forming said dielectric layerin a material comprising silicon oxide.
 44. The method of claim 37,further comprising the step of forming said gate dielectric layer in amaterial comprising silicon oxynitride.
 45. The method of claim 37,further comprising the step of forming said gate dielectric layer in ahigh permittivity material selected from the group consisting of La₂O₃,HfON, Al₂O₃, HfO₂ and ZrO₂.
 46. The method of claim 45, wherein saidhigh permittivity material has a relative permittivity of at least 5.47. The method of claim 37, further comprising the step of forming saidgate dielectric layer to a thickness between 3 Å and 100 Å.
 48. Themethod of claim 37, further comprising the step of forming a differentthickness of said dielectric layer on the sidewall surfaces and on thetop surface of the fin.
 49. The method of claim 37, further comprisingthe step of forming said gate dielectric layer to a smaller thickness onthe top surface of the fin compared to the gate dielectric layer on thesidewall surfaces of the fin.
 50. The method of claim 37, furthercomprising the step of forming the gate dielectric layer on the topsurface of the fin to a thickness of less than 20 Å.
 51. The method ofclaim 37, further comprising the step of forming said gate in a materialcomprising poly-crystalline silicon.
 52. The method of claim 37, furthercomprising the step of forming said gate in a material comprisingpolysilicon germanium.
 53. The method of claim 37, further comprisingthe step of forming said source or drain region in a lightly doped orextension region.
 54. The method of claim 37, further comprising thestep of forming a layer of a conductive material on top of said sourceand drain regions.
 55. The method of claim 54, further comprising thestep of forming said layer of conductive material in a material selectedfrom the group consisting of metal, metallic silicide and metallicnitride.
 56. A method for fabricating a multiple-gate semiconductorstructure comprising the steps of: providing a substrate comprising of asemi-conducting layer overlying an insulating layer; patterning andforming a fin in said semi-conducting layer, said fin having twosidewall surfaces and a top surface; forming a depression in a topsurface of the substrate at a base of said fin; depositing a layer of adielectric material overlying said fin; depositing a layer of aconductive material overlying said layer of dielectric material;patterning said layer of conductive material forming a gate straddlingacross said two sidewall surfaces and said top surface of the fin; andforming a source and a drain region in said semi-conducting layer. 57.The method for fabricating a multiple-gate semiconductor structureaccording to claim 56, further comprising the step of forming saidsemi-conducting layer in a material comprising silicon.
 58. The methodfor fabricating a multiple-gate semiconductor structure according toclaim 56, further comprising the step of forming said semi-conductinglayer in a material comprising silicon and germanium.
 59. The method forfabricating a multiple-gate semiconductor structure according to claim56, further comprising the step of forming said layer of dielectricmaterial in a material comprising silicon oxide.
 60. The method forfabricating a multiple-gate semiconductor structure according to claim56, wherein said fin forming step further comprises a fin surfacesmoothing step.
 61. The method for fabricating a multiple-gatesemiconductor structure according to claim 60, wherein said fin surfacesmoothing step further comprises sub-steps all sacrificial oxidation andhigh temperature annealing in a hydrogen ambient.
 62. The method forfabricating a multiple-gate semiconductor structure according to claim56, further comprising the step of forming said depression in said topsurface of the substrate by undercutting at the base of the fin.
 63. Themethod for fabricating a multiple-gate semiconductor structure accordingto claim 62, further comprising the step of forming said depression byundercutting using an etch process.
 64. The method for fabricating amultiple-gate semiconductor structure according to claim 56, furthercomprising the step of forming said gate dielectric layer in a materialcomprising silicon oxide.
 65. The method for fabricating a multiple-gatesemiconductor structure according to claim 56, further comprising thestep of forming said gate dielectric layer in a material comprisingsilicon oxynitride.
 66. The method for fabricating a multiple-gatesemiconductor structure according to claim 56, further comprising thestep of forming said gate dielectric layer in a high permittivitymaterial selected from the group consisting of La₂O₃, HfON, Al₂O₃, HfO₂and ZrO₂.
 67. The method for fabricating a multiple-gate semiconductorstructure according to claim 66, wherein said high permittivity materialhas a relative permittivity of at least
 5. 68. The method forfabricating a multiple-gate semiconductor structure according to claim56, further comprising the step of forming said gate dielectric layer toa thickness between 3 Å and 100 Å.
 69. The method for fabricating amultiple-gate semiconductor structure according to claim 56, furthercomprising the step of forming a different thickness of the gatedielectric layer on the sidewall surfaces and on the top surface of thefin.
 70. The method for fabricating a multiple-gate semiconductorstructure according to claim 56, further comprising the step of formingsaid gate dielectric layer to a smaller thickness on the top surface ofthe fin compared to the gate dielectric layer on the sidewall surfacesof the fin.
 71. The method for fabricating a multiple-gate semiconductorstructure according to claim 56, further comprising the step of formingthe gate dielectric layer on the top surface of the fin to a thicknessof less than 20 Å.
 72. The method for fabricating a multiple-gatesemiconductor structure according to claim 56, further comprising thestep of forming said gate in a material comprising poly-crystallinesilicon.
 73. The method for fabricating a multiple-gate semiconductorstructure according to claim 56, further comprising the step of formingsaid gate in a material comprising polysilicon germanium.
 74. The methodfor fabricating a multiple-gate semiconductor structure according toclaim 56, further comprising the step of forming said source and drainregion in a lightly doped or extension region.
 75. The method forfabricating a multiple-gate semiconductor structure according to claim56, further comprising the step of forming a layer of a conductivematerial on top of said source and drain regions.
 76. The method forfabricating a multiple-gate semiconductor structure according to claim75, further comprising the step of forming said layer of conductivematerial in a material selected from the group consisting of metal,metallic silicide and metallic nitride.